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Data Sheet
A m p l i fy t h e H u m a n E x p e r i e n c e
(R)
Comlinear CLC2058
FEATURES n Unity gain stable n 100dB voltage gain n 5.5MHz gain bandwidth product n 0.5M input resistance n 100dB power supply rejection ratio n 95dB common mode rejection ratio n 4V to 36V single supply voltage range n 2V to 18V dual supply voltage range n Gain and phase match between amps n CLC2058: improved replacement for NJM4558 and MC1458 n CLC2058: Pb-free SOIC-8 APPLICATIONS n Active Filters n Audio Amplifiers n Audio AC-3 Decoder Systems n General purpose dual ampliifer
Dual 4V to 36V Amplifier
Comlinear CLC2058 Dual 4V to 36V Amplifier
General Description
The COMLINEAR CLC2058 is a dual voltage feedback amplifier that is internally frequency compensated to provide unity gain stability. The CLC2058 offers 3.5MHz of bandwidth at a gain of 2. The CLC2058 also features high gain, low input voltage noise, high input resistance, and superb channel separation making it well suited for audio filter applications in set-top-boxes, DVD players, and televisions. The COMLINEAR CLC2058 is designed to operate over a wide power supply voltage range, 2V to 18V (4V to 36V). It utilizes an industry standard dual amplifier pin-out and is available in a Pb-free, RoHS compliant SOIC-8 package.
Typical Application - 2nd Order Low-Pass Audio Filter
R1 20k C1 150pF
Rev 1A
V EE =-12V
C2 22F/25V VIN
R2 10k C5 1000pF
R3 3.3k
C3 0.1F
2(6)
-
4 1(7)
C4 22F/25V VOUT R5 10k
CLC2058
3(5)
+
8
R4 6.8k
V CC =+12V
C6 0.1F
Ordering Information
Part Number CLC2058ISO8X Package SOIC-8 Pb-Free Yes RoHS Compliant Yes Operating Temperature Range -40C to +85C Packaging Method Reel
Moisture sensitivity level for all parts is MSL-1.
(c)2007-2009 CADEKA Microcircuits LLC
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Data Sheet
CLC2058 Pin Configuration
CLC2058 Pin Description
Pin No. 1 Pin Name OUT1 -IN1 +IN1 -VS +IN2 -IN2 OUT2 +VS Description Output, channel 1 Negative input, channel 1 Positive input, channel 1
OUT1 -IN1 +IN1 -V S
1 2 3 4
8 7 6 5
+VS OUT2 -IN2 +IN2
2 3 4 5 6 7 8
Comlinear CLC2058 Dual 4V to 36V Amplifier
Negative supply Positive input, channel 2 Negative input, channel 2 Output, channel 2 Positive supply
Rev 1A
(c)2007-2009 CADEKA Microcircuits LLC
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2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots.
Comlinear CLC2058 Dual 4V to 36V Amplifier
Parameter Supply Voltage Differential Input Voltage Input Voltage Power Dissipation (TA = 25C) - SOIC-8
Min 0
Max 40 (20) 60 (30) 30 (15) 500
Unit V V V mW
Reliability Information
Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Package Thermal Resistance SOIC-8
Notes: Package thermal resistance (qJA), JDEC standard, multi-layer test boards, still air.
Min -65
Typ
Max 150 150 260
Unit C C C C/W
100
Recommended Operating Conditions
Parameter Operating Temperature Range Supply Voltage Range Min -40 4 (2) Typ Max +85 36 (18) Unit C V
Rev 1A
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3
Data Sheet
Electrical Characteristics
TA = 25C, +Vs = +15V, -Vs = -15V, Rf = Rg =2k, RL = 2k to VS/2, G = 2; unless otherwise noted.
Symbol Parameter Conditions
G = +1, VOUT = 0.2Vpp, VS = 5V, Rf = 0 G = +1, VOUT = 0.2Vpp, VS = 30V, Rf = 0 G = +2, VOUT = 0.2Vpp, VS = 5V G = +1, VOUT = 0.2Vpp, VS = 30V G = +2, VOUT = 1Vpp, VS = 5V G = +2, VOUT = 2Vpp, VS = 30V
Min
Typ
4.62 4.86 3.49 3.55 1.25 0.74 5.5
Max
Units
MHz
Frequency Domain Response
UGBWSS BWSS BWLS GBWP Unity Gain Bandwidth -3dB Bandwidth Large Signal Bandwidth Gain-Bandwidth Product VOUT = 0.2V step; (10% to 90%), VS = 5V VOUT = 0.2V step; (10% to 90%), VS = 30V VOUT = 0.2V step 2V step, VS = 5V 4V step, VS = 30V VOUT = 1VRMS, f = 1kHz, G = 2, RL = 10k, VS = 30V > 1kHz, VS = 5V > 1kHz, VS = 30V Channel-to-channel, 500kHz VS = 5V to 30V VCM = 0V VCM = 0V
(1)
Comlinear CLC2058 Dual 4V to 36V Amplifier
MHz MHz MHz MHz MHz MHz ns ns % V/s V/s
Time Domain Response
tR, tF OS SR Rise and Fall Time Overshoot Slew Rate 100 98 12 2.6 2.8
Distortion/Noise Response
THD+N en XTALK VIO Ib IOS PSRR AOL IS CMIR CMRR RIN ROUT VOUT ISOURCE ISINK
Notes: 1. 100% tested at 25C at VS = 15V.
Total Harmonic Distortion plus Noise Input Voltage Noise Crosstalk Input Offset Voltage (1) Input Bias Current (1) Input Offset Current Open-Loop Gain (1) Supply Current
(1) (1)
0.002 10 10 65 1 70 10 80 85 100 100 2.5 12 70 95 0.5 45 4.5 5 400 100
% nV/Hz nV/Hz dB mV nA nA dB dB mA V dB M V V mA mA
DC Performance
Rev 1A
Power Supply Rejection Ratio
DC, RS 10k RL = 2k, VOUT = 1V to 11V Total, RL = +VS = 30V DC, RS 10k
Input Characteristics
Common Mode Input Range (1,3) Common Mode Rejection Ratio Input Resistance Output Resistance Output Voltage Swing (1) Output Current, Sourcing Output Current, Sinking RL = 2k RL = 10k VIN+ = 1V, VIN- = 0V, VOUT = 2V VIN+ = 0V, VIN- = 1V, VOUT = 2V 10 12
(1)
Output Characteristics
13 14 35 60
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4
Data Sheet
Typical Performance Characteristics
TA = 25C, +Vs = +15V, -Vs = -15V, Rf = Rg =2k, RL = 2k to VS/2, G = 2; unless otherwise noted. Non-Inverting Frequency Response
5 G=1 Rf = 0
Inverting Frequency Response
5 G = -1 0 G = -2 G = -5 G = -10
Comlinear CLC2058 Dual 4V to 36V Amplifier
Normalized Gain (dB)
Normalized Gain (dB)
0
G=2 -5 G=5
-5 -10 -15 -20 -25
G = 10 -10 VOUT = 0.2Vpp -15 0.1 1 10 100
VOUT = 0.2Vpp
0.1
1
10
Frequency (MHz)
Frequency (MHz)
Large Signal Frequency Response
5 0
-3dB Bandwidth vs. VOUT
5
Vout = 2Vpp Vout = 4Vpp
4
-5 -10 -15 -20 -25 0.1 1
-3dB Bandwidth (MHz)
Normalized Gain (dB)
3
2
Rev 1A
1
0 10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Frequency (MHz)
VOUT (VPP)
Small Signal Pulse Response
0.15 0.1
Large Signal Pulse Response
3 2
Output Voltage (V)
0.05 0 -0.05 -0.1 -0.15 0 2 4 6 8 10
Output Voltage (V)
1 0 -1 -2 -3 0 2 4 6 8 10
Time (us)
Time (us)
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5
Data Sheet
Typical Performance Characteristics
TA = 25C, +Vs = +5V, -Vs = GND, Rf = Rg =2k, RL = 2k to VS/2, G = 2; unless otherwise noted. Non-Inverting Frequency Response
5 G=1 Rf = 0
Inverting Frequency Response
5 G = -1 0 G = -2 G = -5 G = -10
Comlinear CLC2058 Dual 4V to 36V Amplifier
Normalized Gain (dB)
Normalized Gain (dB)
0
G=2 -5 G=5
-5 -10 -15 -20 -25
G = 10 -10 VOUT = 0.2Vpp -15 0.1 1 10 100
VOUT = 0.2Vpp
0.1
1
10
Frequency (MHz)
Frequency (MHz)
Large Signal Frequency Response
5 0 -5 Vout = 2Vpp -10 -15 -20 -25 0.1 1 10
-3dB Bandwidth vs. VOUT
5
-3dB Bandwidth (MHz)
Vout = 1Vpp
4
Normalized Gain (dB)
3
2
Rev 1A
1
0 0.0 0.5 1.0 1.5 2.0
Frequency (MHz)
VOUT (VPP)
Small Signal Pulse Response
2.65 2.60
Large Signal Pulse Response
4 3.5
Output Voltage (V)
2.55 2.50 2.45 2.40 2.35 0 2 4 6 8 10
Output Voltage (V)
3 2.5 2 1.5 1 0 2 4 6 8 10
Time (us)
Time (us)
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6
Data Sheet
Typical Performance Characteristics
TA = 25C, +Vs = +15V, -Vs = -15V, Rf = Rg =2k, RL = 2k to VS/2, G = 2; unless otherwise noted. Open Loop Voltage Gain vs. Frequency
120 100
Supply Current vs. Temperature
3.2 3
Comlinear CLC2058 Dual 4V to 36V Amplifier
Open Loop Gain (db)
80 60 40 20 RL=2K 0 0.001 0.01 0.1 1 10 100 1000
Supply Current (mA)
2.8 2.6 2.4 2.2 2 -40 -20 0 20 40 60 80 100 120
Frequency (KHz)
Temperature (C)
Maximum Output Voltage Swing vs. Frequency
20
Maximum Output Voltage Swing vs. RL
16 12
Maximum Swing Voltage (V)
Postive Voltage Swing
Output Voltage Swing (V)
15
8 4 0 -4 -8 Negative Voltage Swing -12 -16
10
Rev 1A
5
RL=2K, THD+N<5%
0 0.1 1 10 100
0.1
1
10
Frequency (KHz)
Resistance Load (K)
Input Offset Voltage vs. Temperature
5 4
Input Bias Current vs. Temperature
120 100
Input Offset Voltage (mV)
3 2 1 0 -1 -2 -40 -20 0 20 40 60 80 100 120
Input Bias Current (nA)
80 60 40 20 0 -40 -20 0 20 40 60 80 100 120
Temperature (C)
Temperature (C)
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Data Sheet
Typical Performance Characteristics
TA = 25C, +Vs = +15V, -Vs = -15V, Rf = Rg =2k, RL = 2k to VS/2, G = 2; unless otherwise noted. Supply Voltage vs. Supply Current
2.5 -2.2
Crosstalk vs. Frequency
-50 -55
Comlinear CLC2058 Dual 4V to 36V Amplifier
2.4
ICC
ICC (mA)
2.3
Crosstalk (db)
-2.3
-60 -65 -70 -75 -80
IEE (mA)
2.2
IEE -2.4
2.1
2 2 4 6 8 10 12 14 16 18
-2.5
-85 0.1 1.0
Supply Voltage (+/-V)
Frequency (MHz)
Functional Block Diagram
VCC
- Input + Input Output
Rev 1A
VEE
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Data Sheet
Application Information
Basic Operation Figures 1, 2, and 3 illustrate typical circuit configurations for non-inverting, inverting, and unity gain topologies for dual supply applications. They show the recommended bypass capacitor values and overall closed loop gain equations.
+Vs 6.8F
Power Dissipation Power dissipation should not be a factor when operating under the stated 2k ohm load condition. However, applications with low impedance, DC coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. Guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond it's intended operating range. Maximum power levels are set by the absolute maximum junction rating of 150C. To calculate the junction temperature, the package thermal resistance value ThetaJA (JA) is used along with the total die power dissipation. TJunction = TAmbient + (JA x PD) Where TAmbient is the temperature of the working environment. In order to determine PD, the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. PD = Psupply - Pload Supply power is calculated by the standard power equation.
Output 0.1F 6.8F -Vs RL Rf
G = - (Rf/Rg) For optimum input offset voltage set R1 = Rf || Rg
Comlinear CLC2058 Dual 4V to 36V Amplifier
Input
+ -
0.1F Output 0.1F RL Rf
G = 1 + (Rf/Rg)
Rg -Vs
6.8F
Figure 1. Typical Non-Inverting Gain Circuit
+Vs 6.8F
R1 Input Rg
+ -
0.1F
Rev 1A
Psupply = Vsupply x IRMS supply Vsupply = VS+ - VSPower delivered to a purely resistive load is: Pload = ((VLOAD)RMS2)/Rloadeff The effective load resistor (Rloadeff) will need to include the effect of the feedback network. For instance, Rloadeff in figure 3 would be calculated as:
Figure 2. Typical Inverting Gain Circuit
+Vs 6.8F
RL || (Rf + Rg) These measurements are basic and are relatively easy to perform with standard lab equipment. For design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. Here, PD can be found from
Input
+ -
0.1F Output RL 0.1F 6.8F -Vs
G=1
PD = PQuiescent + PDynamic - PLoad Quiescent power can be derived from the specified IS values along with known supply voltage, VSupply. Load power
Figure 3. Unity Gain Circuit
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9
Data Sheet
can be calculated as above with the desired signal amplitudes using: (VLOAD)RMS = VPEAK / 2 ( ILOAD)RMS = ( VLOAD)RMS / Rloadeff The dynamic power is focused primarily within the output stage driving the load. This value can be calculated as: PDYNAMIC = (VS+ - VLOAD)RMS x ( ILOAD)RMS Assuming the load is referenced in the middle of the power rails or Vsupply/2. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the packages available.
2
Overdrive Recovery An overdrive condition is defined as the point when either one of the inputs or the output exceed their specified voltage range. Overdrive recovery is the time needed for the amplifier to return to its normal or linear operating point. The recovery time varies, based on whether the input or output is overdriven and by how much the range is exceeded. The CLC2058 will typically recover in less than 30ns from an overdrive condition. Figure 6 shows the CLC2058 in an overdriven condition.
Comlinear CLC2058 Dual 4V to 36V Amplifier
10 VIN = 7.5Vpp G=5 5 Input
20
10
Output Voltage (V)
Maximum Power Dissipation (W)
Input Voltage (V)
1.5
0
Output
0
1
-5
-10
SOIC-8
-10 0 10 20 30 40 50 -20
0.5
Time (us)
0 -40 -20 0 20 40 60 80
Rev 1A
Ambient Temperature (C)
Figure 6. Overdrive Recovery Layout Considerations General layout and supply bypassing play major roles in high frequency performance. CaDeKa has evaluation boards to use as a guide for high frequency layout and as an aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: * Include 6.8F and 0.1F ceramic capacitors for power supply decoupling * Place the 6.8F capacitor within 0.75 inches of the power pin * Place the 0.1F capacitor within 0.1 inches of the power pin
Figure 4. Maximum Power Derating
Driving Capacitive Loads Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. Use a series resistance, RS, between the amplifier and the load to help improve stability and settling performance. Refer to Figure 5.
Input + Rf Rg Rs CL RL
Output
* Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance * Minimize all trace lengths to reduce series inductances
Figure 5. Addition of RS for Driving Capacitive Loads
Refer to the evaluation board layouts below for more information.
(c)2007-2009 CADEKA Microcircuits LLC
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10
Data Sheet
Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of these devices: Evaluation Board # CEB006 CLC2058 Products
Comlinear CLC2058 Dual 4V to 36V Amplifier
Evaluation Board Schematics Evaluation board schematics and layouts are shown in Figures 7-9. These evaluation boards are built for dual- supply operation. Follow these steps to use the board in a single-supply application: 1. Short -Vs to ground. 2. Use C3 and C4, if the -VS pin of the amplifier is not directly connected to the ground plane. Figure 8. CEB006 Top View
Rev 1A
Figure 9. CEB006 Bottom View
Figure 7. CEB006 Schematic
(c)2007-2009 CADEKA Microcircuits LLC
www.cadeka.com
11
Data Sheet
Mechanical Dimensions
SOIC-8 Package
Comlinear CLC2058 Dual 4V to 36V Amplifier
Rev 1A
For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free)
CADEKA, the CADEKA logo design, COMLINEAR, the COMLINEAR logo design, and ARCTIC are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright (c)2007-2009 by CADEKA Microcircuits LLC. All rights reserved.
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